1. Technical Field
The present invention relates to an insulated gate semiconductor drive device which can parallel drive a plurality of insulated gate semiconductor elements connected in parallel, uniformly, with a constant current.
2. Related Art
In a power converter corresponding to a large power load, a plurality of insulated gate semiconductor elements formed of IGBTs, MOS-FETs, or the like, for power control are connected in parallel, and a parallel drive of the insulated gate semiconductor elements is carried out. Also, it is proposed in, for example, Japanese Patent Application Publication No. JP-A-2008-103895 that in place of voltage controlling the gates of the insulated gate semiconductor elements, a constant current is supplied to the gates to turn on the insulated gate semiconductor elements, thereby reducing an occurrence of loss and noise when the insulated gate semiconductor elements are turned on.
This kind of power converter 1 is configured including a plurality of drive circuits 3a to 3n which individually drive a plurality of insulated gate semiconductor elements, for example, IGBTs 2a to 2n, respectively, as shown in, for example, FIG. 5. The plurality IGBTs 2a to 2n are provided in parallel with the collectors connected to each other and the emitters connected to each other. A large power load 4 is connected to the collectors connected in parallel of the IGBTs 2a to 2n. 
As an outline configuration of the drive circuit 3a is shown in FIG. 5, each of the plurality of drive circuits 3a to 3n includes a constant current circuit 7 formed of a constant current source 5, which outputs a constant current Io in accordance with a reference voltage Vref, and a current mirror circuit 6 which supplies a current [k·Io] proportional to an output current Io of the constant current source 5 to the gate of the IGBT 2a. Furthermore, the drive circuit 3a is configured including a discharge circuit 8, which grounds the gate of the IGBT 2a and off-operates the IGBT 2a, and a switch circuit 9 which complementarily on/off controls the current mirror circuit 6 and discharge circuit in accordance with a control signal.
The constant current source 5 is configured of an n-channel FET (hereafter abbreviated to an n-FET) 5a and an OP amplifier 5c which controls the gate voltage of the n-FET 5a in accordance with the difference between a reference voltage Vref and a voltage generated in a resistor 5b interposed between the source of the n-FET 5a and a ground line. When the value of the resistor 5b is taken to be Rref, the output current Io of the n-FET 5a configuring the constant current source 5, by being controlled by the OP amplifier 5c, is made constant as:Io=Vref/Rref
Also, the current mirror circuit 6 is configured of a p-channel FET (hereafter abbreviated to a p-FET) 6a, connected to the constant current source 5, which is driven by the output current Io of the constant current source 5, and a p-FET 6b provided paired with the p-FET 6a. The p-FET 6b assumes the role of supplying a constant current [k·Io] proportional to the constant current Io to the gate of the IGBT 2a. 
Also, the discharge circuit 8 is configured of a buffer 8a, which inputs a control signal, and an n-FET 8b which on/off operates by being gate controlled by the buffer 8a and discharges electric charge accumulated in the gate of the IGBT 2a. Furthermore, the switch circuit 9 is configured of a p-FET 9a connected in parallel to the p-FET 6b of the current mirror circuit 6 and a level shift circuit 9b which turns on/off the p-FETs 6a and 6b of the current mirror circuit 6 by level shifting the control signal and controlling the gate voltage of the p-FET 9a. 
When the control signal is at an L level, the switch circuit 9 turns off the discharge circuit 8 and turns on the p-FET 9a. By so doing, the constant current [k·Io] is supplied to the gate of the IGBT 2a via the p-FET 6b of the current mirror circuit 6, and the IGBT 2a is turned on. Also, when the control signal is at an H level, the switch circuit 9, by turning off the p-FET 9a, stops the current supply to the gate of the IGBT 2a via the current mirror circuit 6, and turns on the n-FET 8b of the discharge circuit 8. By so doing, the electric charge accumulated in the gate of the IGBT 2a is discharged, and the IGBT 2a is turned off.
According to the drive circuit 3a configured in this way, as the constant current is supplied to the gate of the IGBT 2a to turn on the IGBT 2a, the speed of charging the electric charge accumulated in the gate of the IGBT 2a can be made constant. Consequently, according to the drive circuit 3a, it does not happen that the charging speed of the gate of an IGBT varies due to a change in on resistance depending on the temperature of the IGBT, as in a heretofore known common drive method whereby the gate voltage of the IGBT is controlled to turn on/off the IGBT. Therefore, with the drive circuit 3a, the turn-on time of the IGBT 2a can be made constant regardless of a temperature change, and it is thus possible to reduce loss and noise when the IGBT 2a is turned on.
However, as previously described, when the drive circuits 3a to 3n parallel drive the plurality of IGBTs 2a to 2n connected in parallel, there is fear that a current flows concentratedly through an IGBT having a low gate threshold voltage even though each IGBT 2a to 2n is hypothetically turned on by being supplied with the constant current, as heretofore described. Incidentally, variations in the gate threshold voltages of the IGBTs 2a to 2n are due to the solidity of the IGBTs. This kind of current concentration on a specific IGBT when the plurality of IGBTs 2a to 2n are turned on brings about the risk of causing a thermal breakdown of the IGBT.
As heretofore known, therefore, it is proposed, as disclosed in, for example, Japanese Patent Application Publication No. JP-A-11-235015 (also referred to herein as “PTL 2”), that gate current values of the plurality of IGBTs 2a to 2n are measured and stored in advance, and the gate currents of the IGBTs 2a to 2n are controlled based on the gate current values, thus achieving a current balance. Also, it is proposed in, for example, Japanese Patent Application Publication No. JP-A-2008-178248 (also referred to herein as “PTL 3”), that an equipotential offset is given to the drive control voltages and emitter voltages of the IGBTs 2a to 2n in accordance with the difference between a target gate threshold voltage and the gate threshold voltages of the IGBTs 2a to 2n, and further, that the turn-on timings of the IGBTs 2a to 2n are aligned by the equipotential offset, thereby achieving a current balance.
In the technique shown in each PTL 2 and PTL 3, however, it is necessary to obtain the respective gate current values or gate threshold voltages of the plurality of IGBTs 2a to 2n in advance. Moreover, it is necessary to individually control the gate currents of the IGBTs 2a to 2n in accordance with IGBT characteristic data obtained in advance. Alternatively, it is necessary to offset control the respective drive control voltages and emitter voltages of the IGBTs 2a to 2n. Therefore, in the heretofore known technique, there is the problem that regulation requires time and effort, and in addition, the configuration is complicated.